Code Compression for DSP
Charles R. Lefurgy, Trevor Mudge · 1998
Previous works have proposed adding compression techniques to a variety of architectural styles to reduce instruction memory requirements. It is not immediately clear how these results apply to DSP architectures. DSP instructions are longer and have potentially greater variation which can decrease compression ratio. Our results demonstrate that DSP programs do provide sufficient repetition for compression algorithms. We propose a compression method and apply it to SHARC, a popular DSP architecture. Even using a very simple compression algorithm, it is possible to halve the size of the instruction memory requirements. Keywords: Compression, Code Density, Code Space Optimization, DSP, Embedded Systems 1 1 Introduction Architectures for digital signal processing (DSP) have adopted several characteristics of Very Long Instruction Word (VLIW) architectures, including wide instruction words. The cost of using the explicit parallelism of VLIW is much larger code sizes. Beyond the classica...