Formal verification of the Pentium/sup /spl reg//4 floating-point multiplier
Roope Kaivola, Naren Narasimhan · 2003
We present the formal verification of the floating-point multiplier in the Intel IA-32 Pentium/sup /spl reg// 4 microprocessor. The verification is based on a combination of theorem-proving and BDD based model-checking tasks performed in a unified hardware verification environment. The tasks are tightly integrated to accomplish complete verification of the multiplier hardware coupled with the rounder logic. The approach does not rely on specialized representations like binary moment diagrams or its variants.