Statistical modeling for a 0.6 μm BiCMOS technology
J.A. Power, Sean C. Kelly, E.C. Griffith, D. Doyle, Mike O'Neill · 2002
A methodology enabling the generation of accurate statistical circuit simulator (SPICE-level) parameter sets for a 0.6 /spl mu/m BiCMOS process is described. Conventional MOS and BJT parameter extraction practices are too time-consuming to be a realistic option for the construction of the required statistical SPICE parameter database. In this work, accurate relationships are derived between E-Test (WAT) parameters and SPICE-level parameters. Typically E-Test data is routinely monitored and readily available while SPICE-level parameters are much more difficult and expensive to obtain.