Matrix computation on Connex Parallel Architecture
Ana-Maria Calfa, Ștefan Gheorghe · ICSES 2010 International Conference on Signals and Electronic Circuits · 2010
The parallel Connex Architecture has specific features imposed in order to improve GIPS/Watt and GIPS/mm2. It is designed for embedded computation in systems on chip design. Its validation supposes exploring by turn different application domains to see how the specific architectural and design assumptions affected the actual performance. In this paper the domain of matrix computation is preliminary investigated.