Generating verifiable microprocessors state machine code with HDL design tools
R. W. Wall, L.R. Wall · 2004
The ability to verify state machines using HDL synthesis tools for PLD and FPGA devices has outpaced microcontroller development environments. By using a standard program, an arbitrary state machine can be implemented using a microcontroller that has been specified and verified using HDL tools. The size of the state machine is scalable without increasing the amount of processor code. Since the state variable can reside in volatile memory space, the state machine size and requirements can be easily and quickly changed via a network using a standard file structures generated by industry standard tools. An example is provided to demonstrate the process.