Bi-level image high speed code conversion processor: ImPC2
H. Horie, Hideyuki Shirai, Yasuo Iizuka, M. Takahata · 2002
This paper describes a very high speed coding and decoding processor, Image Pipeline Codec 2 (ImPC2), which includes the redundancy reduction coding algorithms: Modified Huffman (MH), Modified RAED (MR), Modified MR (MMR) and JBIG. The ImPC2 architecture combines pipeline and parallel processing. The ImPC2 contains a resolution conversion unit, a DMA controller, 4096/spl times/16-bit RAM, and a microprogram controller with 4096/spl times/50-bit program ROM, as well as a specific encoder and decoder for MH, MR, MMR and JBIG. The ImPC2 chip is fabricated using 0.6 micron CMOS technology, integrating approximately 1,060,000 transistors on a 9.17 mm/spl times/8.50 mm die.