SDV/sup 2/: dynamic visualization of VERILOG simulations
R. Marczynski, P.-M. Seidel · 2003
Gives an introduction to SDV/sup 2/ (SMU Dynamic Verilog Visualization), a software tool for dynamic visualization of Verilog simulations currently developed at SMU. Conventional Verilog simulators focus on computing and displaying waveforms for selected signal values over time. The SDV/sup 2/ tool additionally allows to schematically visualize the module structure of a system described in Verilog and to animate signal propagations between module interfaces as dynamic transitions in the schematics. The dynamic visualization enhances conventional debugging of systems developed in Verilog hardware description language and simplifies the understanding of their dynamic behavior, which is useful both in educational and in industrial settings. In this paper we are describing the basic functionality of the SDV/sup 2/ tool and we give some insight regarding the implementation structure.