A BS-BIST test circuit design for VAD-SOC
Jianfeng Li, Zhang Jinyi, Jiao Li, Yan Laijin · 2004
Along with the more complicated integrated circuit system and the emergence of intelligent properties (IP-based) system on a chip (SOC) system, the test of IC system becomes more difficult and faces new challenge. In this paper we design a BS-BIST test circuit after studying built in self test (BIST) and boundary-scan (BS) technique respectively. At the base of increasing little of cost in circuit complexity, it combines video add data (VAD) SOC to overcome many problems in the test of IP-based SOC system.