Pipe: a high performance VLSI architecture
James E. Smith, Andrew R. Pleszkun, Randy Howard Katz, James R. Goodman · Minds at UW (University of Wisconsin) · 1983
The pipe architecture (parallel instructions and pipelined execution) is proposed as a research vehicle for studying high performance VLSI architectures and organizations. Principal features are: 1) it is pipelined, 2) it is capable of a decoupled mode of operation where two processors cooperate in executing the same task and communicate via hardware queues, 3) it has an instruction cache, and 4) it has a memory interface that allows overlap of memory transactions. This paper describes the proposed architecture and its planned implementation. Included are a discussion of design considerations for a pipelined VLSI architecture, and a description of the particular architecture we have chosen to study. 18 references.