A DSP architecture for motion estimation accelerating
Chun Zhang, Kun Yang, Songping Mai, Zhihua Wang · 2005
Motion estimation (ME) consumes the majority of computation capacity of a DSP in video compression applications. A modified DSP architecture, to accelerate ME algorithms, is presented in this paper. The proposed SIMD and VLIW architecture is a trade-off between ASIC implementation and DSP implementation of ME, which can perform subtract, absolute and add (SAA) operations on 8 pixels and fetch 8 new pixels from memory at the same time. A flexible align addressing mode is provided to support efficient and continuous SAA operation on a video stream. The DSP is estimated to be 20 times faster than the SISD architecture in performing ME algorithms.