Some observations on multiplierless implementation of linear phase FIR filters
M. Bhattacharya, T. Saramäki · 2003
This paper investigates the case of multiplierless implementation of linear phase FIR filters by converting the multiplier coefficients to minimum signed powers-of-two (MNSPT) or canonic signed digit (CSD) forms. It was observed that if one is willing to accept some deviation from the given specifications, the required number of nonzero bits becomes quite low, making multiplierless implementation feasible. Alternatively, one can start with a filter that exceeds the given criteria that may involve an acceptable level of increase in the filter order, but with much lesser total number of nonzero bits than the initial design. Then, the coefficient values are quantized into the desired representation forms such that the given overall criteria are still met. Fairly exhaustive investigation suggests that less than three nonzero bits are quite sufficient, along with reduction in number of arithmetic operations with attendant increase in rate of data throughput.