A 1 GHz Alpha microprocessor
B.J. Benschneider, Sungho Park, R. Allmon, Warren R. Anderson, M. Arneborn, Jang Ho Cho, Changjun Ghoi, J. Clouser, Sangok Han, R. Hokinson, Gyoo‐Cheol Hwang, Daesuk Jung, Jaeyoon Kim, Jean-Michel Krause, JaeHyuk Kwack, S. Meier, Yongsik Seok, Stephen C. Thierauf, C. Zhou · 2002
A 6-way out-of-order issue custom VLSI implementation of the Alpha architecture runs at >1 GHz. The 13.1/spl times/14.7 mm/sup 2/ die contains 15.2 M transistors and utilizes 0.18 /spl mu/m CMOS which includes 7 aluminum interconnect layers and flip-chip packaging. The design of this chip is highly leveraged from an existing 0.35 /spl mu/m, 6-way issue, 6 metal layer implementation with wire-bond packaging technology. The chip contains two on-chip cache arrays; a 64 kB 2-way set associative instruction cache and 64 kB 2-way set associative dual-ported data cache.