Routing chip based on a modified trie for ATM, IP and Ethernet
Deni Torres-Román, A. Larios, M. Guzmán · 2003
This paper presents the design for a routing table circuit for Ethernet-, IP- and ATM-applications. The block architecture is explained. Selection principles of the hardware-implemented algorithm for the routing table circuit control are explained, such as a modified trie with its operations in order to achieve a high performance. The circuit, which can support a flow of 400 Mbps, is connected to the PCI bus and stores 64 K addresses. For the implementation a FLEX10K100 from Altera Company was used.