Dynamic mixed serial–parallel content addressable memory (DMSP CAM)
Mingu Kang, Jisu Kim, Young Hwi Yang, Seong‐Ook Jung · International Journal of Circuit Theory and Applications · 2011
SUMMARY A novel dynamic mixed serial–parallel content addressable memory (DMSP CAM) is proposed to achieve both low‐power consumption and high performance. The replica circuits provide optimal timings to enable and disable the matchline charge transistor, which maximizes performance and minimizes leakage current, respectively. The DMSP CAM does not suffer from charge sharing in the serial stage and achieves high performance by removing the predischarge or precharge operation of the matchline before every comparison. To guarantee the robustness of the proposed scheme, a statistical design methodology is also applied. Using the 45‐nm technology, the DMSP CAM achieves both energy saving and performance improvement, and thus over 53% energy‐delay product reduction compared with the other serial–parallel mixed CAMs. Copyright © 2011 John Wiley & Sons, Ltd.