Bit-level systolic array for FIR filter using AND-based bit-serial multiplier
Jaejin Lee, Gi-Yong Song · 2004
The paper proposes a bit-level systolic array for FIR digital filter with an AND-based bit-serial pipelined multiplier inside. Compared to the conventional systolic array for FIR filter based on word-level data flow, the bit-level systolic array for FIR filter is very compact in that it needs only two 1-bit I/O ports in addition to reduced area requirement without time penalty on the output sequence.