A high performance SSL IPSEC protocol aware security processor
David A. Carlson, D. Brasili, A. Hughes, Amit Jain, T. Kiszely, P. Kodandapani, A. Vardharajan, Thucydides Xanthopoulos, V. Yalala · 2003
A 64M transistor security macro processor enables 40k full SSL handshakes per second with 1024 b RSA. The 3DES, AES, ARC4, SHA-1, MD5 and modular exponentiation cryptographic primitives are also supported. The processor is fabricated in a 0.13 /spl mu/m 8M CMOS process and consumes 12 W at 500 MHz.