A low-PDP and low-area repeater using passive CTLE for on-chip interconnects
Ming-Shuan Chen, Mau-Chung Frank Chang, Chih-Kong Ken Yang · 2015
This paper presents an improved repeater circuit that preserves the advantages of the inverter repeater and achieves a lower power, delay, and area by applying proper equalization. Designed and measured in 65nm CMOS technology, the proposed repeater achieves 44% lower power-delay product (PDP) while occupies 46% lower area.