A reconfigurable multiprocessor IC for prototyping of real-time data paths
D.C. Chen, Jan M. Rabaey · 2003
In real-time digital-signal processing systems, data often enter or leave the computationally intensive parts at small integer multiples of the clocking interval. In these cases, traditional microprocessor-based architectures are inadequate to meet the throughput requirements, and so clusters of dedicated data paths, hard-wired to closely match the algorithmic data flow, are often used. These architectures typically contain multiple concurrently operating data-path pipelines. The circuit reported targets the rapid implementation and prototyping of such architectures using reconfigurable multiprocessors. This circuit contains eight execution units (EXUs) connected via a dynamically controlled crossbar switch. It can operate at 25 MHz (200 MIPs) with a data I/O bandwidth of 400 MB/s and a typical power consumption of 0.45 W. It contains 140106 transistors on a 8.9*9.5 mm/sup 2/ die, in 1.2- mu m CMOS technology.>