An 80 k-transistor configurable 25 MPixels/s video compression processor unit
S. Molloy, Brian Schoner, A. Madisetti, Rajeev Jain · 2002
To address the varied requirements of portable video applications, new processor units are required that can execute a variety of intraframe coding algorithms in real-time. Furthermore, low complexity is required, as the intraframe coder is only one element of the complete video compression system. Neither programmable video signal processors (VSPs) nor dedicated ASICs can satisfy all of the above needs. The video compression processor unit (VCPU) described in this paper is based on a configurable architecture. An efficiency comparison is presented between this processor unit, a programmable VSP E33 and three dedicated video ASICs.>