A novel multiprocessor cache memory
Xiapu Luo, Jon C. Muzio · 2002
A reliable high-performance multiprocessor cache memory that has a reasonable hardware cost is proposed. Using VLSI technology, this cache has a single dual-port directory to deal with the interference between processor operations and data coherence operations in a multiprocessor cache for high performance at low cost. This cache has a protocol-independent structure so that any of the standard data coherence protocols can be implemented. The authors discuss the designs in the cache management unit for fault-tolerance and concurrent checking to increase the cache reliability.>