VLSI architectures for dynamic time warping using systolic arrays
F. Jutand, Nicolas Demassieux, D. Vicard, Gérard Chollet · 2005
Dynamic Time Warping is implemented using an array of identical processing elements. Each processing element is designed to compute a local distance and update a global measure of dissimilarity. It is made up of 1900 transistors using a 2.5 micron NMOS technology. 25 processing elements and their local interconnections fit within 35mm2 of silicon that can be packaged in a standard 40 pin packaging. A single chip can handle 300 words in real time. An array of 22 chips will recognize within 200msec a syllable size pattern from a set of 6000. Various applications are taken up.