A 50 MHz uniformly pipelined 64 b floating-point arithmetic processor
B.J. Benschneider, William J. Bowhill, E.M. Cooper, Moshe Gavrielov, P.E. Gronowski, Vijayshri Maheshwari, Victor Peng, J.D. Pickholtz, Sridhar Samudrala · 2003
A description is given of a uniformly pipelined, 50-MHz, 64-b floating-point arithmetic processor implemented in a 1.5- mu m (drawn) CMOS technology which performs single- and double-precision floating-point operations and integer multiplication as defined by a superminicomputer architecture standard. The chip is composed of an interface section and a five-segment execution core. The core insists of a divider, bypassed in all instruction except division, and four fully pipelined stages that are uniformly utilized in the execution of all instructions. The performance is summarized. First pass silicon has been functionally verified at 50 MHz with a set of over one million vectors.>