Behavioral synthesis : digital system design using the Synopsys Behavioral Compiler
David W. Knapp · 1996
1. Introduction. Design Flow. Simulation and Verification. RTL and Behavioral Design. Behavioral Compiler Design Flow. 2. Behavioral Compiler. Inputs. Behavioral Compilation: Internals. 3. HDL Descriptions. The Design. Behavioral Processes. Clock and Reset. I/O Operations. Flow of Control. Memory Inference. synthetic Components. Preserved Functions. Pipelined Components. Random Logic. 4. I/O Modes. Cycle-Fixed Mode. Superstate-Fixed Mode. Free-Floating Mode. Control Unit Registers. 5. Explicit Directives and Constraints. Labeling. Scheduling Constraints. Options. Test Benches Simulation. 6. Reports. Timing Report. Reservation Tables. State Machine Reports. Error Messages. 7. FIR Filter. Initial Design. Synthesis. Simulation. Decreasing Cost. 8. IIR Filter: Handshaking I/O Protocal. Initial Design. Simulation. Synthesis. Speeding Up the Clock. 9. The Inverse Discrete Cosine Transform: C to HDL. Initial C Code. Translation into HDL. Simulation. 10. The Data Encryption Standard: Random Logic. General Description. HDL Description. Synthesis. Use of Design Ware. 11. Packet Router. A. Construction Design Ware. B. Sythesizable Subsets.