FVP: a formal verification platform for SoC
Wen-Shiu Liao, Pao‐Ann Hsiung · 2004
How to verify a system-on-a-chip (SoC) has been an important issue in the SoC design process due to its complexity. The capacity of traditional verification techniques such as simulation or emulation is no longer suitable for SoCs. However, formal verification that provides 100% coverage and counterexamples is expected to be a complementary solution. Several researches on formally verifying an SoC have demonstrated its feasibility and benefits. Nevertheless, there is no utility for platform-based formal verification of SoCs as yet. A formal verification platform (FVP) is proposed to formally verify an intellectual property (IP) by providing a formal platform to create its environment. We illustrate our modeling experiences using the model checker SGM.