Simulation based system level fault insertion using co-verification tools
Bill Eklow, Amir Hossein Hosseini, Chi Khuong, S. Pullela, Toai Vo, Henry Hoi Ki. Chau · 2005
This work presents a simulation-based, fault insertion environment, which allows faults to be "injected" into a Verilog model of the hardware. A co-verification platform is used to allow real, system level software to be executed in the simulation environment. A fault manager is used to keep track of the faults that are inserted on to the hardware and to monitor diagnostic messages to determine whether the software is able to detect, diagnose and/or cope with the injected fault. Examples be provided to demonstrate the capabilities of this approach as well as the resource requirements (time, system, human). Other benefits and issues of this approach also be discussed.