Distributed CRC Architecture for High-Radix Parallel Turbo Decoding in LTE-Advanced Systems
Hyeji Kim, Injun Choi, Wooseok Byun, Jong-Yeol Lee, Ji-Hoon Kim · IEEE Transactions on Circuits & Systems II Express Briefs · 2015
This brief presents two types of distributed cyclic redundancy check (CRC) architecture for a high-radix parallel turbo decoder in LTE/LTE-advanced communication systems. The conventional CRC architecture in the parallel turbo decoder requires both huge timing overhead and energy waste since the CRC of the message is calculated after completion of the soft-input soft-output (SISO) decoding process or concurrently with the next SISO decoding, even though the message is already confirmed for its integrity. The distributed CRC architecture proposed in this brief computes the CRC while the message is decoded separately, and it can provide the stopping signal to the decoder with negligible computing latency after completion of the SISO decoding process. The two proposed architectures are based on Galois field arithmetic and implemented in a 65-nm CMOS process where various block sizes, degrees of parallelism, and radix numbers of the high-radix SISO decoder are supported.