A complete 0.5 μm high performance array family
Y.S. Yung · 2002
A 3.3 V CMOS gate array and embedded array family with 0.5 /spl mu/m drawn channel length and three metal layers has been developed for high performance applications. With internal toggle frequency at 600 MHz, this array family can be designed to handle over 100 MHz, and even up to 200 MHz system speed. In addition, high speed I/O's, tight clock skew control methodology, embedded macros and high performance BGAs are developed to provide designers a complete solution for high speed system designs.