An ECL RISC microprocessor designed for two level cache
David Roberts, T. Layman, George S. Taylor · 2002
RISC architectures by virtue of their streamlined instruction set and more efficient use of fundamental machine resources are capable of exploiting emerging VLSI technologies more quickly than traditional, more complicated, machine architectures. This paper describes the recently announced MIPS R6000, R6010 and R6020 ECL chip set, which provides further evidence of the validity of this argument.>