Hierarchical Intellectual Property Protection Using Partially-Mergeable Cores
Vikram Iyengar, Hiroshi Date, Makoto Sugihara, Krishnendu Chakrabarty · 2001
this paper, we present a novel technique to separate critical-IP modules or cores lying within a core from the low-IP part of the parent core. Critical-IP modules are dened as those modules whose internal structure is unconditionally required to be hidden from the core user. Even within the company designing a core, access to the internal structure of critical-IP modules may often be restricted to only a few design engineers [8]. Protection of these IP modules during test development is therefore vital. Low-IP modules, on the other hand, refer to the modules and gates whose internal structure can be made known to the core user. Critical-IP modules are guaranteed to be protected 100% by our technique. Moreover, our technique also separates out and therefore protects a large portion of the low-IP modules. The core provider adds a built-in self test (BIST) wrapper to test the IP-protected part of the core. Since the core provider has complete access to the gate-level model of the core, test point insertion for BIST can readily be done before the core is provided to the user