Lazy Retirement: A Power Aware Register Management Mechanism
Guillermo Savransky, Ronny Ronen, Antonio M. González · 2002
In this paper we describe a poweraware improvement to the Intel’s P6 family microarchitecture. Lazy Retirement significantly reduces the energy and power involved in register retirement. Lazy Retirement delays the copy from the physical register file (ROB) to the architectural (real) register file (RRF) until it has no choice and the physical register has to be re-used. In many cases, a new retired instruction invalidates such register before it is needed to be copied. Overall, Lazy Retirement eliminates most of the register copy operations involved in register retirement – saving energy while incurring no performance degradation. Alternatively, the reduction in register accesses can be used to decrease the number of register ports thus allowing even faster, less complex, and more energy efficient register file – with a minimal performance loss. Results: Lazy Retirement eliminates about 75% of retirement-related register copies in typical integer code. Lazy Retirement enables the reduction in the number of retirement-related register file ports from 3 to 2 with practically no performance penalty or even from 3 to 1 with very minor performance penalty.