Reducing Conflict Misses in Caches
Pepijn J. de Langen, Ben H. H. Juurlink · 2003
Nearly all modern computing systems employ caches to hide the memory latency. Modern processors often employ multiple levels of cache, with one or more levels on the same die as the processor core. As performance demands increase, it becomes increasingly important for an on-die cache structure to perform well. Inefficient use of the available cache space can become increasingly costly in terms of both speed [1] and power usage [4]. Speed and size constraints often make the case for small on-die caches, with little or no associativity. However, small direct-mapped caches may result in a large number of conflict misses.