Area-time optimal vlsi integer multiplier with minimum computation time
Kurt Mehlhorn, Franco P. Preparata · Lecture notes in computer science · 1983
According to VLSI theory, [log n, √n]is the range of computation times for which there may exist an AT2-optimal multiplier of n-bit integers. Such networks were previously known for the time range [Ω(log2 n), O(√n)]; this theoretical question is settled, by exhibition of a class of AT2-optimal multipliers with computation times [Ω(log n), O(√n)]. The designs are based on the DFT on a Fermat ring, whose elements are represented in a redundant radix-4 form to ensure O(1) addition time.