Accelerating CMOS Device Model Evaluation Using Multi-FPGA Systems
Ahmed Maache, Jeff S. Reeve, Mark Zwoliński · ePrints Soton (University of Southampton) · 2009
Recently, FPGAs have been integrated into HPC clusters in order to boost their computational performance while reducing the power consumption significantly. EDA tools and algorithms are example applications which are demanding more computational power due to the current increase in complexity of analogue and mixed-signal chips. This made transistor-level simulation a growing bottleneck in the integrated circuit development process. This paper discusses the design and implementation of an FPGA-based reconfigurable system to accelerate the SPICE CMOS LEVEL 3 model device evaluation. The preliminary results showed that the system demonstrated an average speed improvement of up to 12x faster than a software implementation running on an Intel 2.0 GHz based workstation. This result is based on a single FPGA implementation. The paper also outlines the design of the multi-FPGA system to accelerate the CMOS model. The proposed system can be attached as a high speed co-processor to boost the SPICE simulation performance.