A 32 × 32 cellular test chip targeting new functionalities
A. Paasio, Mika Laiho, Asko Kananen, Kari A. I. Halonen, Jussi H. Poikonen · 2003
In this paper the design of a cellular computer with 32/spl times/32 cells is discussed by referencing to different points of alternatives for realizing massively parallel analogue processor arrays. The design is a combination of cellular nonlinear network type computing and an analog microprocessor. Motivations are given for the selected solutions that are used to implement a test chip with a resolution of 32/spl times/32 cells. Digital solutions are used in the 32/spl times/32 design to mitigate the effect of traditional bottlenecks in computing speed, namely analog weight programming and analog I/O. Furthermore, as A/D/A converters are included in each cell, alternative solutions for analog storage are highlighted.