Self-Timed Architecture of a Reduced Instruction Set Computer
I. David, Ran Ginosar, Michael Yoeli · 1993
An advanced Self-Timed Reduced Instruction Set Computer (ST-RISC) architecture is described. It is designed hierarchically, and is formally specified functionally at the various levels by a CSP-like language. The architectural features include decoupled data and branch processors, delayed branches with variable delay, unified data path and control, efficient non-redundant handshaking protocols, and novel self-timed building blocks such as combinational logic, master-slave registers, finite state machines, and FIFO elements. Keywords: Asyncronous systems, computer architecture, high-level synthesis, reduce instruction set computer, self-timed. 1. Introduction The design and construction of an asynchronous computer is relatively a complex task. Asynchronous design of digital circuits is not as straightforward as synchronous design; the former refrains from the relaxing assumptions and external enforcement of timing available with clocked systems. While synchronous implementations of digi...