A CMOS VLSI analog current-mode high-speed ART1 chip
T. Serrano, B. Linares-Barranco, J.L. Huertas · 2002
Presents a real time neural categorizer chip based on the ART1 algorithm. The circuit implements a modified version of the original ART1 algorithm more suitable for VLSI implementations. It has been designed using analog current-mode circuit design techniques, and consists basically of current mirrors that are switched on and off according to the binary input patterns. The chip is able to cluster 100 binary pixels input patterns into up to 18 different categories. Modular expandability of the system is possible by simply interconnecting more chips in a matrix array. This way a system can be built to cluster N/spl times/100 binary pixels images into M/spl times/18 different clusters, using an N/spl times/M array of chips. Average pattern classification is performed in less than 1 /spl mu/s, which means an equivalent computing power of 1.8/spl times/10/sup 9/ connections per second. The chip has been fabricated in a single-poly double-metal 1.5 /spl mu/m standard digital low cost CMOS process, has a die area of 1 cm/sup 2/, and is mounted in a 120 pins PGA package.>