VLIW architectures for low–power processors: A first evaluation
Jean-Michel Puiatti, Eduardo García Sánchez, Christian Piguet, Josep Llosa · Infoscience (Ecole Polytechnique Fédérale de Lausanne) · 1998
In this paper, we evaluate the possibility of designing a high-performance, low-consumption 8b or 16b microcontroller. More precisely, we investigate whether the instruction-level parallelism (ILP) architectures (e.g., superscalar or VLIW) used in high-performance, high-consumption processors can be adapted to low-power, high-performance 8b or 16b microcontrollers. In order to quantify the potential improvements that can be obtained by these kinds of parallel architectures, we make a comparison between low-power scalar processors and low-power ILP processors in terms of both performance and energy efficiency.