A CMOS Matrix-Vector Multiplier (MAVEM) with Self-Testing Capabilities
N. Kanopoulos, J. Bergschneider · European Solid-State Circuits Conference · 1983
This paper describes a Si-gate CMOS Matrix-Vector multiplier with self-testing (on-line) capabilities. This multiplier multiplies a 3×3 matrix with a 3 element vector and outputs their product. The word size for the chip is 8-bits, and all the operations are done bit-serially. All the events in the chip are synchronized with a 4 MHz two-phase clock, and the system interfaces directly with a 6MHz microprocessor. A self-testing scheme incorporated into the design allows fault detection and isolation concurrently with the data processing.