Cache design for high performance computers with BiCMOS VLSIs
M. Morioka, K. Kurita, Hiroaki Kobayashi, Hideo Sawamoto · 2002
Cache memory architectures and BiCMOS circuit technologies for high-speed access time that take advantage of the high integration level are discussed. Proposed is a VLSI-oriented cache memory architecture, which reduces the penalty of chip-crossings, and a functional BiCMOS RAM with gate-array suited to the associative function of the cache memory. BiCMOS cache chip sets are developed for high-performance computers with 0.8- mu m BiCMOS technology. The BiCMOS cache memory can improve the cost-performance of cache systems due to high-speed access time and high density.>