Novel bit manipulation unit for communication digital signal processors
Sung‐Dae Kim, Sug Hyun Jeong, Myung Hoon Sunwoo, Kyung-Ho Kim · 2004
This paper proposes application-specific instructions and their bit manipulation unit (BMU), which efficiently support scrambling, convolutional encoding, puncturing, and interleaving. The proposed DSP employs the BMU supporting parallel shift and XOR (Exclusive-OR) operations and bit insertion/extraction operations on multiple data. The proposed architecture has been modeled by VHDL and synthesized using the SEC 0.18 /spl mu/m standard cell library and the gate count of the BMU is only about 1700 gates. Performance comparisons show that the number of clock cycles can be reduced about 40%/spl sim/80% for scrambling, convolutional encoding and interleaving compared with existing DSPs.