A custom instruction approach for hardware and software implementations of finite field arithmetic over F//sub 2/sup163// using Gaussian normal bases
Marcio Juliato, Guido Costa Souza De Araujo, Julio López, Ricardo Dahab · 2006
In this paper we explore the potential use of custom instructions in a reconfigurable hardware platform to accelerate arithmetic operations in the binary field F/sub 2163/ using a Gaussian normal basis representation. System-on-chip (SOC) techniques based on field programmable gate arrays (FPGAs) are used, making it possible to run real applications on the system while considering all execution overheads. Thus we are able to fairly compare hardware and software performances, as well as precisely determine their speedups. Using this approach, we show that a field multiplication can be accelerated over 2619 times when implemented in hardware. Moreover, using this fast field multiplier in a hardware/software approach, we accelerate point multiplication, the fundamental operation of ECC, over 116 times.