Register‐Transfer Level Design
Andrew Rushton · 2011
Logic synthesis works on register-transfer level (RTL) designs. What logic synthesis offers is an automated route from an RTL design to a gate-level design. This chapter outlines the basic steps in the RTL methodology. It is recommended that these basic steps are used when designing for logic synthesis. To illustrate the connection between RTL and logic synthesis, the examples are written in very-high speed integrated circuits programme (VHSIC) hardware description language (VHDL). The basic design steps in using RTL are: identify the data operations, determine the type and precision of the operations, decide what data processing resources to provide, allocate operations to resources, allocate registers for intermediate results, design the controller, and design the reset mechanism. The VHDL model of the RTL design can be simulated and checked against the system design. Controlled Vocabulary Terms controllers; hardware description languages; Integrated circuit synthesis; very high speed integrated circuits