The Prospects for On-Line Hybrid Coherency Protocols on Bus-Based Multiprocessors
Jack E. Veenstra, Robert J. Fowler · 1994
Since data access patterns vary from application to application, neither write-invalidate nor write-update is the better strategy for maintaining cache coherence in all cases. Thus, it may be advantageous to use a hybrid cache coherency protocol that combines the best aspects of each. Although write-invalidate is the dominant approach in commercial multiprocessors, the recent introduction of coalescing write buffers combined with relaxed models of memory consistency can be expected to improve the performance of protocols based on updating. This motivates our reexamination of the relative performance of write-invalidate, write-update, and on-line dynamic hybrid protocols. Using a detailed program-driven simulation of a high-performance bus-based multiprocessor with release-consistent caching, we compare the performance of several variations on the hybrid protocol used in DEC AXP multiprocessors with the performance of several more conventional protocols. The variations on the hybrid pro...