A 750 Mb/s 0.6 μm CMOS two-phase input port using self-tested self-synchronization
Fenghao Mu, Christina Svensson · 2003
As clock frequency on silicon chips increases continuously, clock phase becomes difficult to control or predict. A method of self-tested self-synchronization, STSS-2, is implemented by a two-phase input port for parallel/series data transfer between modules. In 0.6 /spl mu/m CMOS, a data rate of 750 Mb/s is reached with 3.6 V power supply. There is no need for a test signal, and synchronization is achieved by using the timing relation between the local clock and incoming data.