An energy-efficient FPGA-based soft-core processor with a configurable word size ECC arithmetic accelerator
Aiko Iwasaki, Yuichiro Shibata, Kiyoshi Oguri, Ryuichi Harasawa · 2015
This paper proposes an FPGA-based soft core processor architecture equipped with a configurable accelerator to speed up GF(2m) arithmetic for elliptic curve cryptography (ECC) systems. Focusing on the fact the number of operations required for GF(2m) arithmetic is influenced by the relationship between the irreducible polynomial and the machine word size, we propose an approach where the word size of the accelerator is tailored to a given irreducible polynomial. The evaluation results reveal that the performance and the energy efficiency of GF(2m) multiplication including reduction can be improved by up to 6.67 times and 5.24 times, respectively.