Implementation of systolic/wavefront processor arrays using single-chip digital signal processors
K.H. Yu, Yu Hen Hu · 2003
The exploitation of the high computational power and programmability of commercial single-chip digital signal processors is proposed to implement systolic/wavefront arrays. Systolic/wavefront arrays are viewed as special cases of general-purpose multiprocessing arrays and interconnection hardware which facilitates autonomous data/control communication is proposed. A prototype of a wavefront array using 4 TMS32020s, capable of performing high-speed matrix multiplication computations, is presented.>