Application specific memories for ATM packet switching
Alex G. Dickinson, Chris Nicol, S. Koteswara Rao, M. Hatamian · 2002
The constrained data access patterns occurring within memory-based packet switches permit the design of application specific SRAM devices that may outperform generic SRAM parts in switch applications. We describe two such devices: one reads and writes a single location in a single 10 ns cycle; the other uses a systolic approach to pipeline accesses in a large array resulting in a 5 ns cycle time.>