Using IEEE P1149.4
J.S. Matos, José Machado da Silva · 2002
This paper reviews the special needs posed by today's technological advances in boards and MCMs, and addresses the requirements they place on design for testability techniques for assemblies of complex chips, both digital and mixed-signal. The IEEE P1149.4 mixed-signal test infrastructure is briefly described and its use as a means to support and implement different DfT techniques is described. Actual results are shown of its use on the implementation of a mixed current/voltage testing technique.