Design Space Exploration for Networks On-chip
Francisco Gilabert Villamón · 2011
7 Example of library with a switch and a NI . . . . . . . . . . . .5.8 Optimal placement of target and initiator a) for a write transaction and b) for a read transaction. . . . . . . . . . . . . . . .5.9 Core placement algorithm . . . . . . . . . . . . . . . . . . . . .5.10 Candidate calculation for optimal and suboptimal sets of candidate templates for different system sizes. . . . . . . . . . . . .5.11 Flow diagram of the simulation engine. . . . . . . . . . . . . . .5.12 Performance results of a DSE for an SoC with 36 cores. . . . .5.13 Example of core definition in CEF format. . . . . . . . . . . . .5.14 Place and route at 1 mm inter-switch spacing at a target speed of 1 GHz (IP Core size not drawn to scale). . . . . . . . . . . .5.15 Place and route at 1.5 mm inter-switch spacing at a target speed of 1 GHz (IP Core size not drawn to scale). . . . . . . . . . . .5.16 Place and route at 3 mm inter-switch spacing at a target speed of 1 GHz (IP Core size not drawn to scale). . . . . . . . . . . .5.17 Cell distribution of a core. . . . . . .