A 1.8 V 64 Mb 100 MHz flexible read while write flash memory [in CMOS]
Bharat M. Pathak, Anthony Ramos Cabrera, G. Christensen, A. Darwish, M. Goldman, Rezaul Haque, James L. Jorgensen, R.S. Kajley, T. Ly, F. Marvin, S. Monasa, Quan M. Nguyen, Donald G. Pierce, A. Sendrowski, I. Sharif, H. Shimoyoshi, A. Smidt, Rammohan Sundaram, M. Taub, WENDY U. TRAN · 2002
A flash memory with flexible multi-partition architecture allows programming or erasing in one partition while reading from another partition. The 64 Mb memory uses a 0.18 /spl mu/m process that has a 0.32 /spl mu/m/sup 2/ cell. The device has 18 ns asynchronous page mode access and synchronous burst reads up to 100 MHz with zero wait state.